Remember when every new AI milestone came with a photo of one enormous square of silicon, held up like a trophy? For years the story of faster AI was basically the story of bigger, denser single chips. One slab, one design team, one very long wait between generations.
That story is quietly changing. The new interest is in breaking the big chip into smaller pieces called chiplets, and then designing those pieces and the system they live in at the same time. That second part has a name: co-design. And according to recent research, it cuts both the energy AI accelerators burn and the cost of designing them in the first place.
What a chiplet actually is
Think of a traditional processor as a single-piece plastic toy, molded in one go. If you want a slightly different version, you need a whole new mold. Chiplets are the Lego approach instead. You make a handful of smaller blocks, each good at one thing, and snap them together into whatever shape the job needs.
One block might handle math. Another might handle memory. Another might move data between the rest of them. Because they are separate, you can mix and match, reuse them across products, and swap one out without redesigning everything around it.
The co-design part is where the savings hide
Here is where it gets interesting for anyone who cares about AI costs rather than transistor trivia. Historically, chip pieces and the surrounding package were designed somewhat separately, handed off between teams. Co-design means optimizing them together, treating the connections, the power delivery, and the layout as part of the same problem.
A technical paper out of the University of Michigan, published in September 2026, lays out a framework for exactly this and reports meaningful reductions in both energy use and design cost. The framework’s selling points are power efficiency and design flexibility, which sounds abstract until you remember those are the two things that usually trade off against each other. Efficient chips tend to be rigid. Flexible chips tend to waste power. Doing the design work jointly loosens that knot.
Other research points the same direction. A project called Fengshui looked at what happens when you build a small shared pool of chiplets rather than custom-designing everything. With just eight co-optimized chiplets, covering different data-handling styles, processing-in-memory, and network switches, the reported energy reduction was 48.5 percent, alongside larger improvements on related efficiency measures that combine energy with delay.
Eight building blocks. Roughly half the energy. That is the kind of number that makes hardware people sit up.
Why this matters if you never touch a chip
You might reasonably wonder why a non-technical reader should care about packaging strategy. Two reasons.
- Energy is the ceiling on AI, not ideas. At Chiplet Summit 2026, Dr. Nasrullah framed the problem as AI’s 10GW challenge and presented four design techniques for addressing it, including node mixing, which means combining chiplets built on different manufacturing generations instead of forcing everything onto the newest and most expensive one. When people discuss AI’s power appetite in terms of gigawatts, the design of the chips stops being a niche engineering topic.
- Design cost shapes who gets to build. Designing a large custom chip is brutally expensive, which is why so few organizations do it. Lower the design cost and the list of players who can build specialized AI hardware gets longer. More competition at the hardware layer eventually reaches you as cheaper inference, which is to say cheaper AI agents doing the work you asked them to do.
This is not just a lab idea
The ecosystem is being built out in public. The U.S. CHIPS National Advanced Packaging Manufacturing Program explicitly includes chiplet ecosystems and co-design in its scope, which signals that the modular approach is treated as infrastructure rather than an experiment. On the commercial side, Cadence offers chiplet platform solutions aimed at the business and engineering problems companies hit when they try to design this way. Tooling and public funding tend to show up when an approach is heading toward normal.
The honest caveat
Modularity has a cost. Every time you split a chip into pieces, the connections between those pieces become a place where power gets spent and performance gets lost. Co-design is the response to that problem, not a way of pretending it does not exist. The reason these frameworks get attention is that they appear to solve more than they cost, and the reported numbers are about efficiency gains, not about making the underlying physics easier.
For those of us explaining AI to people who just want to know what changes, the short version is this. The next round of AI hardware improvement may come less from making one giant chip bigger and more from getting smarter about how the smaller pieces are chosen and connected. Less monument, more Lego set. And if the energy figures hold up, that is the more useful kind of progress.
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